What is Gate-All-Around (GAA) — and Why Did the Transistor Just Change for the First Time in a Decade?

What a transistor actually does — and why geometry matters. A transistor is an electrically controlled switch. It controls whether current flows between two terminals (the source and drain) by applying voltage to a third (the gate). Every logic operation, memory read, and AI inference computation reduces to billions of these switches toggling on and off. The geometry of the switch determines how cleanly it can turn off — and how much current leaks through it when it should be off. That leakage is the primary driver of heat and wasted power in chips.

FinFET, introduced by Intel at 22nm in 2012, solved the leakage problem of that era by standing the silicon channel up as a vertical “fin” and wrapping the gate around three of its four sides. That extra gate contact — versus the single top surface of the prior planar transistor — dramatically improved control. FinFET carried the industry for 13 years. Its limit became visible below 3nm: as the fin narrows, the one uncovered side of the channel becomes a leakage path that the three-sided gate cannot suppress.

What GAA changes — and the physics behind it. Gate-All-Around replaces the vertical fin with multiple thin horizontal silicon nanosheets stacked above each other. The gate material completely encloses each nanosheet on all four sides, providing 360-degree electrostatic control of every channel layer. When the gate voltage says “off,” there is no uncovered face left for leakage current to escape through.

The naming varies by company: TSMC calls its implementation nanosheet GAA or GAAFET; Samsung calls its variant Multi-Bridge-Channel FET (MBCFET); Intel calls its version RibbonFET. The transistor physics is identical in each case — full gate encirclement of the channel. What differs is how each foundry stacks the nanosheets, their dimensions, and integration with surrounding metal layers. These differences translate directly into the yield, density, and power efficiency claims each foundry makes for its respective node.

TSMC N2: what the numbers actually mean. TSMC’s N2 node entered volume production in Q4 2025, ramping across Fab 20 and Fab 22 in Hsinchu and Kaohsiung — its first GAA process. Compared to N3E, TSMC claims 10–15% performance gain at the same power, 25–30% power reduction at equivalent performance, and 15–20% higher transistor density. SRAM yield reached over 90% on 256-megabit test blocks — an unusually strong early signal that the node is maturing faster than previous transitions.

Apple has confirmed N2 for its A-series chip family. AMD’s Venice EPYC server processors are in N2 production ramp. MediaTek confirmed a flagship SoC tape-out on N2 with volume production targeted for end-2026. N2P — a performance-enhanced variant — and A16, which adds TSMC’s “Super Power Rail” backside power delivery, both entered production in H2 2026. Backside power routes power through the rear of the wafer, freeing front-side tracks for signal routing and improving both density and power efficiency — critical for large AI and HPC chips.

Samsung and Intel: the other two GAA players. Samsung Foundry pioneered GAA at 3nm (SF3, mass production June 2022), predating TSMC’s adoption by over three years. Its 2nm SF2 first generation entered mass production in Q4 2025 using the Exynos 2600 as its inaugural commercial chip. A second-generation SF2 with backside power delivery began ramping in H2 2026, competing directly with TSMC’s A16.

Intel’s 18A uses RibbonFET combined with PowerVia — its backside power delivery — making it the only 2nm-class node that shipped with backside power from day one. Intel entered 18A production in 2025 for its Panther Lake processors but has attracted limited external customer interest. The practical conclusion for 2026–27: TSMC N2 and Samsung SF2 are the only two GAA nodes with confirmed volume external commercial production. Intel’s 14A in 2027 is when foundry analysts expect it could begin closing that gap.

What comes after the transistor — backside power delivery. GAA’s arrival is accompanied by a second architectural change that matters more to AI silicon than to smartphones: backside power delivery. In conventional chips, both signal wires and power rails share the front surface. At high transistor densities, power routing consumes so much front-side space that signal routing suffers. Backside power delivery moves power rails to the rear of the silicon wafer, freeing the front entirely for signals.

Intel integrated PowerVia into 18A from day one. TSMC’s A16 adds “Super Power Rail” to the N2 transistor base — and the combination of GAA transistors with backside power is expected to be the preferred process for next-generation AI accelerators, TPUs, and HPC processors. Routing congestion at those workload scales makes front-side power a binding constraint that GAA transistors alone cannot solve. TSMC’s A16 is the node most industry analysts identify as the first process technology specifically optimised for AI chip requirements from the transistor level up.

Three predictions for 2027–28. First: TSMC A16 (GAA plus backside power) will prove more consequential for AI silicon than N2 itself. NVIDIA’s post-Rubin architecture and the next generation of Google TPUs are the most likely first flagship AI chips on A16, since large AI accelerators benefit disproportionately from backside power’s routing improvements. The performance delta between N2 and A16 at HPC die sizes will exceed the N3E-to-N2 improvement TSMC cites for standard logic.

Second: Samsung SF2 Gen2 wins a marquee non-Samsung design win in 2027 — the most likely candidate is a hyperscaler custom ASIC program seeking supply chain diversification. Samsung’s competitive pitch will increasingly rely on price and lead time rather than process specifications. Third, and most contrarian: Intel’s 18A achieves no meaningful external production volume in 2027. Its RibbonFET transistor is technically credible, but the yield maturity, EDA tool ecosystem, and fabless customer confidence needed to displace TSMC for production silicon at scale remains beyond Intel’s 2027 execution horizon. The real Intel test is 14A.