What is a Custom AI Chip, and Why Are Google, Amazon and Meta All Building Their Own?

What a custom AI chip actually is. A custom AI chip — formally an application-specific integrated circuit, or ASIC — is an accelerator designed for one company's specific AI workloads rather than bought off the shelf. Instead of a general-purpose GPU optimised to run any model, an ASIC is tuned to the exact shapes of the models a hyperscaler already runs at massive, predictable scale.

Google began this journey in 2016 with its first Tensor Processing Unit, built to accelerate TensorFlow inference across search and ads. The economic case then was cost; the case in 2026 is the same, amplified. Google's current Ironwood TPU delivers 4.7 times the compute of its predecessor. Meta's MTIA 400 — built on RISC-V, not ARM — delivers 6 petaflops of FP8 compute, purpose-tuned for the recommendation systems driving Facebook and Instagram's ad revenue. Amazon's Trainium4 supports 288 GB of memory per instance and counts Anthropic and OpenAI as early training customers.

Why every hyperscaler wants one. The economics resolve into three arguments. First, cost: a hyperscaler that runs one known model at billion-inference-per-day scale can design a chip tuned exactly to its memory access patterns, number formats, and data flow. The result is a 30–50% reduction in cost-per-inference versus NVIDIA hardware for the specific models it serves, per independent analyst estimates.

Second, control: a hyperscaler that designs its own chip is not subject to NVIDIA's allocation decisions, lead times, or pricing power. The GPU rationing of 2022–23, when H100s were effectively waitlisted, validated the strategic case in a way no business case could. Third, fit: the HBM base-die customisation now available in HBM4E means memory can be co-designed with the compute die — a level of integration impossible when buying a merchant GPU off a product sheet.

The duopoly enabling it all. Hyperscalers have the AI expertise to define what a chip should do. Translating that into manufacturable silicon requires specialised knowledge of physical implementation, timing closure, and advanced packaging that only two companies currently deliver at scale: Broadcom and Marvell. Together they control roughly 95% of the custom AI ASIC co-design market.

Broadcom's roster reads like a hyperscaler roll-call — Google's TPU (confirmed through 2031), Meta's MTIA, Microsoft's Maia, and in 2026, OpenAI's Titan accelerator program. In February 2026, Broadcom taped out the first 2nm custom compute system-on-chip using its 3.5D packaging technology. CEO Hock Tan has stated "line of sight" to $100 billion in AI chip revenue by 2027, backed by a $73 billion disclosed backlog.

Marvell, MediaTek, and the cracks in the duopoly. Marvell holds the counter-position: Amazon's Trainium processors, Microsoft's Maia (jointly with Broadcom), and a growing AI data-processing unit portfolio. In March 2026, NVIDIA invested $2 billion in Marvell through a NVLink Fusion arrangement — integrating Marvell's custom silicon with NVIDIA's interconnect fabric, a tacit acknowledgment that custom and merchant chips will co-exist in the same cluster rather than compete in separate ones.

The first crack in the duopoly arrived at MediaTek's April 2026 earnings call: the Taiwanese IC design house announced its first AI accelerator program for a major US hyperscaler, guiding $2 billion in AI ASIC revenue for Q4 2026 alone. That entry signal — a credible third design partner entering the market — is the most underreported development in custom silicon this year.

Where NVIDIA fits in the new order. NVIDIA's response to the custom silicon wave reveals what the wave actually is. Jensen Huang's strategic emphasis on sovereign AI, national compute infrastructure, and enterprise AI explicitly targets markets where no hyperscaler ASIC exists — governments, universities, healthcare, defence. For research teams whose model architectures change monthly, there is no point designing an ASIC; you need a programmable GPU that can retrain tomorrow on a different architecture. NVIDIA remains dominant there.

What has genuinely shifted is the inference layer — the high-volume, fixed-model serving workload where ASIC economics are compelling. The 2026 data-centre accelerator market exceeds $200 billion. NVIDIA capturing 63% of $200 billion earns more revenue than capturing 88% of the $60 billion market it dominated in 2023. The ASIC wave is a market-expansion narrative that redistributes the marginal dollar of new growth, not a threat to the incumbent's absolute revenue.

Asia is where all of this gets made. The custom silicon shift has a supply chain that is almost entirely Asian. TSMC fabricates chips for all five major hyperscaler ASIC programs — every chip in the Exhibit 2 table goes through Hsinchu or Tainan. The CoWoS advanced packaging that integrates compute dies with HBM adds another dependency on TSMC's Taichung and Chiayi facilities. SK hynix, Samsung and Micron supply HBM for every chip in the table. The ASIC wave does not reduce Asia's centrality to AI compute — it deepens it, because ASIC economics only work when yields are high, and high yields for advanced custom silicon require mature CoWoS relationships that only TSMC currently offers.

MediaTek's entry as a co-design partner is the most significant emerging development for the regional industry. If MediaTek wins a second hyperscaler, it breaks the Broadcom-Marvell lock and redistributes design revenue toward Taiwan — the only Asia-based company currently competing at the ASIC co-design tier.

Three predictions for 2026–27. First: by end-2027, custom ASIC volume shipments exceed GPU volume shipments for AI inference — Counterpoint and Broadcom guidance both converge there. Second: a fourth credible co-design partner emerges at scale. MediaTek's US hyperscaler win is the signal; if it delivers on schedule, it becomes the template for the Korean design houses (Samsung LSI, SK hynix logic) to follow. Third: NVIDIA's NVLink Fusion strategy succeeds — Marvell's custom chips become interoperable with NVIDIA's interconnect fabric, and hybrid ASIC-GPU clusters become the dominant AI data-centre architecture by late 2027.

The honest counterpoint. Custom silicon has real limits. ASICs are brittle: a chip tuned for one model architecture becomes expensive to retrain for the next. Meta's strategy — a new MTIA generation every six months — is a candid admission that model evolution is fast enough to stress any custom silicon roadmap. The companies most exposed to that brittleness are the ones betting most aggressively: a multi-billion ASIC program that serves the wrong model architecture for 18 months is a sunk cost, not a strategic asset. NVIDIA's CUDA flexibility is not just lock-in — it is genuine insurance against architectural bet risk that ASICs cannot replicate.